Title :
A retiming-based test pattern generator design for built-in self test of data path architectures
Author :
El-Maleh, Aiman H. ; Osais, Yahya E.
Author_Institution :
Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
Abstract :
Recently, a new Built-In Self Test (BIST) methodology based on balanced bistable sequential kernels has been proposed that reduces the area overhead and performance degradation associated with the conventional BILBO-oriented BIST methodology. This new methodology guarantees high fault coverage but requires special test sequences and test pattern generator (TPG) designs. In this paper, we demonstrate the use of the retiming technique in designing TPGs for balanced bistable sequential kernels. Experimental results on ISCAS benchmark circuits demonstrate the effectiveness of the designed TPGs in achieving higher fault coverage than the conventional maximal-length LFSR TPGs
Keywords :
automatic test pattern generation; built-in self test; fault diagnosis; logic testing; sequential circuits; timing; BIST; ISCAS benchmark circuits; area overhead; balanced bistable sequential kernels; built-in self test; data path architectures; fault coverage; retiming technique; retiming-based test pattern generator; test sequences; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Kernel; Logic testing; Registers; Test pattern generators;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922296
