Title :
Bit-level pipelined digit serial GF(2m) multiplier
Author :
Ibrahim, M.K. ; Almulhem, A.
Author_Institution :
King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
Abstract :
A low latency digit serial multiplier for GF(2m) that can be pipelined to the bit-level is presented in this paper. Unlike existing structures, the new multiplier does not put any restriction on the type of generator polynomial used or the digit size. Furthermore, the latency of the new multiplier is significantly less than the latency of the existing bit-level pipelined digit-serial multiplier
Keywords :
Galois fields; multiplying circuits; pipeline arithmetic; polynomials; bit-level pipelined digit serial GF(2m) multiplier; digit size; finite field arithmetic; generator polynomial; latency; Arithmetic; Cryptography; Delay; Error correction codes; Galois fields; Hardware; Minerals; Petroleum; Pipeline processing; Polynomials;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922305
