DocumentCode
1745303
Title
Effectivity of standby-energy reduction techniques for deep sub-micron CMOS
Author
van der Meer, P.R. ; van Staveren, A.
Author_Institution
Electron. Res. Lab., Delft Univ. of Technol., Netherlands
Volume
4
fYear
2001
fDate
6-9 May 2001
Firstpage
594
Abstract
Present and future transistor technologies suffer from increasing standby leakage. In this paper the effectivity of standby-energy reduction techniques will be expressed in terms of a minimum required standby time. Beyond this time the corresponding standby-energy reduction is profitable for the specific application. Techniques known from literature are evaluated in the context of GSM and UMTS applications. The Triple-S technique is shown to be able to double the standby time of a UMTS application
Keywords
CMOS integrated circuits; leakage currents; low-power electronics; GSM; Triple-S technique; UMTS; deep submicron CMOS IC; standby energy reduction; standby leakage; standby time; transistor technology; 3G mobile communication; CMOS digital integrated circuits; CMOS process; CMOS technology; Diodes; Energy dissipation; Information processing; Information technology; Leakage current; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.922307
Filename
922307
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