Title :
High-speed CMOS logic circuits in capacitor coupling technique
Author :
Huang, Hong-Yi ; Wang, Teng-Neng
Author_Institution :
Dept. of Electron. Eng., Fu-Jen Univ., Taiwan
Abstract :
A pipelined four-phase logic circuit called the CMOS capacitor coupling logic (C3L) circuit is proposed. The operation of the pipelined system is described. A folding technique is used for the XOR gate design. A carry look-ahead adder (CLA) is designed using the capacitor coupling technique. Using the technique, the device count and the power dissipation can be reduced. The simulation of a full adder and a CLA in 0.35 μm process shows that the maximum operating speed can reach 400 MHz
Keywords :
CMOS logic circuits; adders; carry logic; high-speed integrated circuits; multivalued logic circuits; pipeline processing; 0.35 micron; 400 MHz; C3L circuit; XOR gate design; capacitor coupling technique; carry look-ahead adder; device count; folding technique; full adder; high-speed CMOS logic circuits; operating speed; pipelined four-phase logic circuit; power dissipation; Adders; CMOS logic circuits; CMOS memory circuits; Capacitors; Clocks; Coupling circuits; Logic circuits; Logic devices; Logic functions; Voltage;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922317
