• DocumentCode
    1745310
  • Title

    Efficient power clock generation for adiabatic logic

  • Author

    Mahmoodi-Meimand, H. ; Afzali-Kusha, Ali

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Tehran Univ.
  • Volume
    4
  • fYear
    2001
  • fDate
    6-9 May 2001
  • Firstpage
    642
  • Abstract
    Practical issues in the design of power clock generators needed by adiabatic logic circuits are explained. Synchronous and asynchronous power clock generators are designed for an 8-bit adiabatic carry look-ahead adder and the more energy efficient circuit for the power clock generation is determined to be the 2N synchronous power clock generator that exhibits conversion efficiency of 77% at 10 MHz operating frequency
  • Keywords
    adders; clocks; logic circuits; 10 MHz; 77 percent; 8 bit; adiabatic logic circuit; asynchronous power clock generator; carry look-ahead adder; conversion efficiency; energy efficiency; synchronous power clock generator; Adders; CMOS logic circuits; Clocks; DC generators; Degradation; Logic circuits; Power generation; RLC circuits; Synchronous generators; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
  • Conference_Location
    Sydney, NSW
  • Print_ISBN
    0-7803-6685-9
  • Type

    conf

  • DOI
    10.1109/ISCAS.2001.922319
  • Filename
    922319
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1745310