Design of an efficient FFT processor for DAB system

Author

Lo, Hsin-Fu ; Shieh, Ming-Der ; Wu, Chien-Ming

Author_Institution

Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

654

Abstract

This paper describes the design of Fast Fourier Transform (FFT) for the Eureka-147 DAB system. We investigate several possible FFT implementations based on the single butterfly architecture, including an in-place memory structure, to minimize the hardware requirement. We also describe a unified approach toward partitioning the whole memory into several banks so as to increase the equivalent memory bandwidth between the memory unit and the butterfly unit, which can be implemented in either radix-2 or high-radix arithmetic. Implementation results demonstrate the applicability of our work to the targeted channel demodulator and the advantages over previous solutions

Keywords

digital arithmetic; digital audio broadcasting; digital signal processing chips; fast Fourier transforms; Eureka-147 DAB system; channel demodulator; fast Fourier transform processor; hardware design; high-radix arithmetic; in-place memory structure; memory partitioning; radix-2 arithmetic; single butterfly architecture; Bandwidth; Computer architecture; Concurrent computing; Demodulation; Equations; Hardware; Integrated circuit interconnections; Memory management; Processor scheduling;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922322

Filename

922322