Title :
A CAD tool for architecture level exploration and automatic generation of RNS converters
Author :
Soudris, D.J. ; Dasigenis, M.M. ; Vasilopoulou, S.K. ; Thanailakis, A.T.
Author_Institution :
Dept. of Electr. & Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece
Abstract :
The analysis and implementation of a CAD tool that can generate the structural description of converters for the Residue Arithmetic System (RNS), assisting the engineer in the architecture level exploration, is presented. The above description is based on a previous proposed architecture, which has been reported as an efficient known to date in terms of area and delay. The outputs of the tool are: (i) abstract but precise hardware characteristics of the converter being designed in order to have a fast estimation of its efficiency and (ii) a synthesizable structural VHDL description for this converter, which can be the input to a VLSI design environment (e.g. Cadence, Synopsis) in order to take the actual silicon implementation. The proposed tool was implemented in C++ language and is available for PC and HP platforms
Keywords :
C++ language; VLSI; circuit CAD; digital signal processing chips; hardware description languages; high-speed integrated circuits; integrated circuit design; logic CAD; residue number systems; C++ language; CAD tool; Cadence; RNS converters; Synopsis; VLSI design environment; architecture level exploration; area; automatic generation; delay; hardware characteristics; structural description; synthesizable structural VHDL description; Arithmetic; Delay; Design automation; Digital signal processing; Dynamic range; Hardware; Semiconductor device measurement; Silicon; Very high speed integrated circuits; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922341
