A bit-serial column parallel processing architecture for on-sensor discrete Fourier transform

Author

Kawahitio, S. ; Eki, T. ; Tadokoro, Y.

Author_Institution

Res. Inst. of Electron., Shizuoka Univ., Hamamatsu, Japan

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

738

Abstract

Recent advances in CMOS image sensor technology allow us to realize highly-integrated imaging devices. This paper proposes an architecture of discrete Fourier transform (DFT) for integration on the CMOS image sensor. The proposed bit-serial column parallel DFT scheme is suitable for the integrated image sensor from the viewpoints of high-speed processing, cost-effective implementation, and matching with the column parallel A/D conversion architecture of the CMOS imager. In the case of 256×256-point DFT, the processing time is estimated to be 2 ms at clock frequency of 100 MHz, which corresponds to the 500 frame/s real-time processing

Keywords

CMOS image sensors; analogue-digital conversion; discrete Fourier transforms; focal planes; parallel architectures; 100 MHz; 2 ms; A/D conversion architecture; CMOS image sensor technology; bit-serial column parallel processing architecture; clock frequency; high-speed processing; on-sensor discrete Fourier transform; processing time; real-time processing; CMOS image sensors; Circuits; Discrete Fourier transforms; Discrete cosine transforms; Frequency estimation; Image converters; Image processing; Parallel processing; Real time systems; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922343

Filename

922343