Title :
Parallel decoding architectures for low density parity check codes
Author :
Howland, C. ; Blanksby, A.
Author_Institution :
High Speed Commun. VLSI Res. Dept., Agere Syst., Holmdel, NJ, USA
Abstract :
A parallel architecture for decoding low density parity check (LDPC) codes is proposed that achieves high coding gain together with extremely low power dissipation, and high throughput. The feasibility of this architecture is demonstrated through the design and implementation of a 1024 bit, rate-1/2, soft decision parallel LDPC decoder
Keywords :
decoding; error correction codes; parallel architectures; coding gain; low density parity check codes; parallel decoding architectures; power dissipation; soft decision parallel LDPC decoder; throughput; Block codes; Iterative algorithms; Iterative decoding; Parallel architectures; Parity check codes; Power dissipation; Signal processing algorithms; Sparse matrices; Throughput; Turbo codes;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922344
