Title :
Sample-reset loop filter architecture for process independent and ripple-pole-less low jitter CMOS charge-pump PLLs
Author :
Maxim, Adrian ; Scott, Baker ; Schneider, Eric ; Hagge, Melvin ; Chacko, Steve ; Stiurca, Dan
Author_Institution :
Mass Storage Div., Crystal-Cirrus Logic Inc., Austin, TX, USA
Abstract :
This paper presents a low jitter, high resolution frequency synthesizer realized in 0.18 μm CMOS technology, using a novel sample-reset loop filter technique that gives a process independent damping factor, and low jitter operation with minimum ripple filtering pole requirements. PLL specifications include: operating range 125-1270 MHz, resolution <500 KHz, jitter <0.8%·Tosc, and dissipating 75 mW from a 2.5 V supply
Keywords :
CMOS integrated circuits; active filters; frequency synthesizers; jitter; phase locked loops; poles and zeros; 0.18 micron; 125 to 1270 MHz; 2.5 V; 75 mW; CMOS charge-pump PLL; frequency synthesizer; jitter; process independent damping factor; ripple filtering pole; sample-reset loop filter; Active filters; Bandwidth; CMOS process; Capacitance; Charge pumps; Damping; Feedforward systems; Frequency; Jitter; Phase locked loops;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922350
