A new controlled gain phase-locked loop technique

In this paper, a new Controlled Gain PLL (CGPLL) technique is described. The proposed technique is based on an Analog Frequency Detector (AFD) and a Controlled Gain Charge Pump (CGCP). It achieves a fast lock-in time, while simultaneously providing a good stability and a low jitter. The CGPLL, which is a charge-pump type PLL, includes a phase-frequency detector, a CGCP, a low-pass filter, and a Wide Swing Differential Voltage Controlled Oscillator (WSDVCO). The PLL gain adaptation is accomplished by varying the current in the charge pump according to the frequency deviation between the input and VCO output signals. The proposed CGPLL was designed using 0.25 μm CMOS technology. Spectre simulation results show that its lock-in time is 10 times shorter (for the same operating voltage and frequency) than a previously proposed PLL, which is based on the same circuitry, except for the loop adaptation mechanism