A new controlled gain phase-locked loop technique

Author

Fouzar, Y. ; Savaria, Yvon ; Sawan, M.

Author_Institution

Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

810

Abstract

In this paper, a new Controlled Gain PLL (CGPLL) technique is described. The proposed technique is based on an Analog Frequency Detector (AFD) and a Controlled Gain Charge Pump (CGCP). It achieves a fast lock-in time, while simultaneously providing a good stability and a low jitter. The CGPLL, which is a charge-pump type PLL, includes a phase-frequency detector, a CGCP, a low-pass filter, and a Wide Swing Differential Voltage Controlled Oscillator (WSDVCO). The PLL gain adaptation is accomplished by varying the current in the charge pump according to the frequency deviation between the input and VCO output signals. The proposed CGPLL was designed using 0.25 μm CMOS technology. Spectre simulation results show that its lock-in time is 10 times shorter (for the same operating voltage and frequency) than a previously proposed PLL, which is based on the same circuitry, except for the loop adaptation mechanism

Keywords

CMOS integrated circuits; phase locked loops; 0.25 micron; CMOS technology; Spectre simulation; analog frequency detector; controlled gain charge pump; controlled gain phase locked loop; jitter; lock-in time; low-pass filter; phase-frequency detector; stability; wide swing differential voltage controlled oscillator; CMOS technology; Charge pumps; Circuit simulation; Jitter; Low pass filters; Phase detection; Phase frequency detector; Phase locked loops; Stability; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922361

Filename

922361