Title :
Fault isolation in nonlinear analog circuits with tolerance using the neural network-based L1-norm
Author :
He, Yigang ; Sun, Yichuang
Author_Institution :
Sch. of Electr. & Inf. Eng., Hunan Univ., Changsha, China
Abstract :
This paper deals with fault isolation in nonlinear analog circuits with tolerance under an insufficient number of independent voltage measurements. A neural network-based L1-norm optimization approach is proposed and utilized in locating the most likely faulty elements in nonlinear circuits. The validity of the proposed method is verified by both extensive computer simulations and practical examples. One simulation example is presented in the paper
Keywords :
analogue circuits; circuit optimisation; circuit simulation; fault location; fault tolerance; neural nets; nonlinear network analysis; L1-norm optimization; computer simulation; fault isolation; fault tolerance; neural network; nonlinear analog circuit; Analog circuits; Circuit faults; Circuit testing; Fault diagnosis; Fault location; Intelligent networks; Neural networks; Nonlinear circuits; Parameter estimation; Voltage;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922372
