Title :
High-voltage stress test paradigms of analog CMOS ICs for gate-oxide reliability enhancement
Author :
Khalil, Mohammad Athar ; Wey, Chin-Long
Author_Institution :
Dept. of Electr. & Comput. Eng., Michigan State Univ., East Lansing, MI, USA
Abstract :
This paper presents the first-ever research on high-voltage stress of analog circuits to enhance their oxide reliability and to reduce the manufacturing cost. The emphasis of this paper is placed on how to properly stress analog circuits and the development of efficient algorithms for generating stress vectors that meet the stress coverage requirement within a feasible stress time
Keywords :
CMOS analogue integrated circuits; integrated circuit reliability; integrated circuit testing; life testing; production testing; analog CMOS ICs; gate-oxide reliability enhancement; high-voltage stress test paradigms; manufacturing cost; stress coverage requirement; stress time; stress vectors; Analog circuits; Analog integrated circuits; CMOS analog integrated circuits; CMOS digital integrated circuits; CMOS integrated circuits; CMOS process; Circuit testing; Costs; Stress; Voltage;
Conference_Titel :
VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001
Conference_Location :
Marina Del Rey, CA
Print_ISBN :
0-7695-1122-8
DOI :
10.1109/VTS.2001.923458
