DocumentCode
1745591
Title
Direct comparison of electrical performance of 0.1-μm pMOSFETs doped by plasma doping or low energy ion implantation
Author
Lenoble, D. ; Grouillet, A. ; Arnaud, F. ; Haond, M. ; Feich, S.B. ; Fang, Z. ; Walther, S. ; Liebert, R.B.
Author_Institution
CNET, Meylan, France
fYear
2000
fDate
2000
Firstpage
468
Lastpage
471
Abstract
The fabrication of ultra-shallow junctions (USJ) is becoming one of the most challenging tasks for advanced CMOS technology. We experimentally show the limits of the standard ion implantation technique. Then, we demonstrate the benefit induced by the use of the low biased PLAsma Doping (PLAD) processes to fabricate USJ. Next, we have fabricated deep sub-micrometer pMOSFETs. The measured electrical results show that the basic device performance is improved when the source/drain extensions are plasma doped instead of the standard BF2+ implantation. We attribute this improvement to a better control of the lateral spread of the extensions under the gate. This characteristic is directly correlated to the strong reduction of the junction depth when the PLAD technique is used
Keywords
CMOS integrated circuits; MOSFET; doping profiles; ion implantation; plasma materials processing; semiconductor device measurement; semiconductor doping; 0.1 mum; BF2+ implantation; PLAD processes; advanced CMOS technology; deep sub-micrometer pMOSFETs; electrical performance; fabrication; junction depth; lateral spread; low biased plasma doping processes; low energy ion implantation; pMOSFETs; plasma doping; source/drain extensions; ultra-shallow junctions; CMOS technology; Doping; Electric variables measurement; Fabrication; Ion implantation; MOSFETs; Plasma devices; Plasma immersion ion implantation; Plasma measurements; Plasma sources;
fLanguage
English
Publisher
ieee
Conference_Titel
Ion Implantation Technology, 2000. Conference on
Conference_Location
Alpbach
Print_ISBN
0-7803-6462-7
Type
conf
DOI
10.1109/.2000.924189
Filename
924189
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