Title :
On the VLSI area and bisection width of star graphs and hierarchical cubic networks
Author :
Yeh, Chi-Hsiang ; Parhami, Behrooz
Author_Institution :
Dept. of Electr. & Comput. Eng., Queen´´s Univ., Kingston, Ont., Canada
Abstract :
We solve an open question posed by Akers and Krishnamurthy in 1986 concerning VLSI layout of star graphs. We show that the area of the optimal layout of an N-node star graph, hierarchical cubic network (HCN), or hierarchical folded-hypercube network (HFN) is N2/16±o(N2) under the Thompson model, or under the extended grid model where a node occupies a rectangle of sides that may range from n-1 to o(√N) for the n-star, log2N+1 to o(√N) for the HCN, and log2N+2 to o(√N) for the HFN. An n-dimensional star graph this requires less area than any possible layout of a similar-size hypercube, but more than that of the much smaller n-cube. We also derive multilayer layout for star graphs that has area N2/8[L2/2]±o(N 2/L2), where a node occupies a rectangle of sides ranging from [n-1/4] to o(√N/L) and the number L of wiring layers satisfies 2⩽L=o(√N/n). Finally we show that the bisection width of an N-node star graph is N/4±o(N) and the bisection width of an HCN or HFN is exactly N/4
Keywords :
circuit complexity; multiprocessor interconnection networks; N-node star graph; VLSI area; bisection width; hierarchical cubic network; hierarchical cubic networks; hierarchical folded-hypercube network; multilayer layout; star graphs; Computer networks; Fault tolerance; Hypercubes; Multiprocessor interconnection networks; Nonhomogeneous media; Very large scale integration; Wiring;
Conference_Titel :
Parallel and Distributed Processing Symposium., Proceedings 15th International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7695-0990-8
DOI :
10.1109/IPDPS.2001.925019