Updates of the ITRS design cost and power models

Design cost and power/energy have been major challenges for the semiconductor industry over the past decade or more. Increase in gate count, driven by scaling of physical dimensions per Moore´s Law, has dramatically increased the diversity of integrated functions and overall design complexity. To control design cost and schedule in light of limited human and computing resources, design productivity must be continually improved. The International Technology Roadmap for Semiconductors (ITRS) Design Chapter [10], which provides a design technology roadmap to inform the electronic design automation (EDA) industry and internal CAD organizations, has since 2001 maintained a design cost model that tracks implications for SOC design cost of anticipated design productivity improvements. The power/energy challenge stems from a variety of causes, e.g., high-performance functional requirements, non-ideal scaling of supply voltages, interconnect capacitances, and leakage currents. The ITRS Design Chapter has since 2009 also roadmapped low-power design technologies that address the power challenge. This paper provides an updated overview of the ITRS design cost model, as well as the low-power design technology roadmap along with associated technology solutions. Potential design technology solutions to mitigate design cost and power/energy challenges in the coming decade are also noted.