• DocumentCode
    1746830
  • Title

    A low-power 8-PAM serial-transceiver in 0.5 μm digital CMOS

  • Author

    Foley, David J. ; Flynn, Michael P.

  • Author_Institution
    Parthus Technol. plc, Cork, Ireland
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    123
  • Lastpage
    126
  • Abstract
    A CMOS multi-level (8-PAM) transceiver is described. Preemphasis is implemented without an increase in DAC resolution or digital computation. The receiver oversamples with three fully differential 3-bit ADCs. The device transmits at up to 1.3 Gb/s and has a measured BER of <10-13 for an 810 Mb/s PRBS transmission. The device, packaged in a 68 pin CLCC, is implemented in 0.5 μm digital CMOS, occupies 2 mm2 and dissipates 400 mW from a 3.3 V supply
  • Keywords
    CMOS digital integrated circuits; data communication equipment; digital communication; low-power electronics; pulse amplitude modulation; transceivers; 0.5 micron; 3.3 V; 400 mW; 810 Mbit/s; BER; CLCC package; DAC resolution; PRBS transmission; bit error rate; differential ADCs; digital CMOS process; low-power 8-PAM serial-transceiver; multi-level transceiver; oversampling; preemphasis implementation; Bit error rate; CMOS process; Circuits; Clocks; Decoding; Engines; Logic; Packaging; Synthesizers; Transceivers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits, 2001, IEEE Conference on.
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-6591-7
  • Type

    conf

  • DOI
    10.1109/CICC.2001.929738
  • Filename
    929738
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1746830