A low-power digital filter IC via soft DSP

Author

Hegde, Rajamohana ; Shanbhag, Naresh R.

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

fYear

2001

fDate

2001

Firstpage

309

Lastpage

312

Abstract

In this paper we present an integrated circuit implementation of a soft DSP based low-power digital filter in 0.35 μm, 3.3 V CMOS process. Soft DSP is a low-power technique that employs voltage overscaling (VOS) and algorithmic noise-tolerance (ANT) to push the limits of energy-efficiency beyond that achievable by voltage scaling alone. VOS refers to scaling the supply voltage beyond the limit imposed by the throughput constraints. ANT is an algorithmic level error-control technique that is employed to restore the algorithmic performance degradation in terms of output signal-to-noise ratio (SNR) caused by VOS. Measured results indicate 40%-67% reduction in energy dissipation over optimally voltage-scaled systems with less than 1 db loss in SNR for a wide range of filter bandwidths (0.05 f_s-0.25 f_s, where f_s is the sampling frequency)

Keywords

CMOS digital integrated circuits; circuit optimisation; digital filters; digital signal processing chips; low-power electronics; 0.35 micron; 3.3 V; CMOS process; algorithmic level error-control technique; algorithmic noise-tolerance; energy dissipation; energy-efficiency; filter bandwidths; low-power digital filter IC; low-power technique; optimally voltage-scaled systems; output signal-to-noise ratio; sampling frequency; soft DSP; throughput constraints; voltage overscaling; CMOS digital integrated circuits; CMOS integrated circuits; CMOS process; Digital filters; Digital integrated circuits; Digital signal processing; Energy efficiency; Integrated circuit noise; Throughput; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 2001, IEEE Conference on.

Conference_Location

San Diego, CA

Print_ISBN

0-7803-6591-7

Type

conf

DOI

10.1109/CICC.2001.929788

Filename

929788