Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability

Author

Matsumoto, S. ; Mattausch, H.J. ; Ooshiro, S. ; Tatsumi, Y. ; Miura-Mattausch, M. ; Kumashiro, S. ; Yamaguchi, T. ; Yamashita, K. ; Nakayama, N.

Author_Institution

Dept. of Electr. Eng., Hiroshima Univ., Japan

fYear

2001

fDate

2001

Firstpage

357

Lastpage

360

Abstract

We propose an efficient, test-circuit-based method to determine not only CMOS-device-parameter variations but to simultaneously separate intra-chip from inter-chip variations. The method is demonstrated by using a differential-amplifier stage with feedback coupling as the test-circuit and the drift-diffusion MOSFET model HiSIM for the circuit simulation. The result shows that the proposed test circuit, when constructed only with n-MOSFETs or p-MOSFETs, enables one to separate gate length and channel doping variations as well as their inter- and intra-chip magnitudes in a direct way

Keywords

CMOS analogue integrated circuits; MOSFET; circuit simulation; differential amplifiers; feedback amplifiers; integrated circuit design; integrated circuit modelling; integrated circuit reliability; semiconductor device models; CMOS-device-parameter variations; CMOSFETs; HiSIM model; analog-design reliability; channel doping variations; circuit simulation; differential-amplifier stage; drift-diffusion MOSFET model; feedback coupling; gate length variations; inter-chip MOSFET-performance variations; intra-chip MOSFET-performance variations; n-MOSFETs; p-MOSFETs; test-circuit-based extraction; Analog circuits; CMOS technology; Circuit simulation; Circuit testing; Coupling circuits; FETs; Hysteresis; MOSFET circuits; System testing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 2001, IEEE Conference on.

Conference_Location

San Diego, CA

Print_ISBN

0-7803-6591-7

Type

conf

DOI

10.1109/CICC.2001.929801

Filename

929801