A design environment for high throughput, low power dedicated signal processing systems

Author

Davis, W. Rhett ; Zhang, Ning ; Camera, Kevin ; Chen, Fred ; Markovic, Dejan ; Chan, Nathan ; Nikolic, Borivoje ; Brodersen, Robert W.

Author_Institution

California Univ., Berkeley, CA, USA

fYear

2001

fDate

2001

Firstpage

545

Lastpage

548

Abstract

A hierarchical automated design flow for low-energy direct-mapped signal processing integrated circuits is presented. A modular framework based on a combined Simulink and floorplan description drives automatic layout generation. Automatic characterization of layout improves system-level estimates. The flow is demonstrated on the subsystems of CDMA and OFDM receivers and a 300 k transistor test-chip

Keywords

OFDM modulation; application specific integrated circuits; circuit layout CAD; code division multiple access; digital signal processing chips; digital simulation; integrated circuit layout; CDMA; OFDM; Simulink; automatic layout generation; dedicated signal processing systems; floorplan description; hierarchical automated design flow; modular framework; system-level estimates; transistor test-chip; Algorithm design and analysis; Application specific integrated circuits; Computer architecture; Design methodology; Parallel processing; Signal design; Signal processing; Signal processing algorithms; Throughput; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 2001, IEEE Conference on.

Conference_Location

San Diego, CA

Print_ISBN

0-7803-6591-7

Type

conf

DOI

10.1109/CICC.2001.929839

Filename

929839