Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping

Algorithm-to-hardware High-Level Synthesis (HLS) tools are becoming increasingly practical, particularly the domain specific approaches to HLS. Storage allocation is an important step in HLS where variables are mapped to onchip storage structures (OSS). HLS flows almost exclusively do this allocation to random access OSS whereas custom designers often pick from a repertoire of intuitive algorithm-appropriate OSS. In this work, revisiting a sparsely addressed problem of storage allocation to sequential access OSS, we report tractable algorithms for storage allocation to three kinds of sequential access style memories-Queue, Queue-Read Sequential-Write memory (QRSWM), and Sequential-Read Sequential-Write memory (SRSWM)-suitable for domains such as signal processing and matrix computations. A basic C to Verilog HLS flow was developed integrating these new allocations options to evaluate their impact on the overall design metrics of interest such as area and power. On application cases such as matrix multiplication and 2D/3D wavelet filtering, a comparison vis-a-vis RAM shows significant improvements in power consumption when targeting TSMC 0.18μ technology.