HW/SW partitioning for region-based dynamic partial reconfigurable FPGAs

With dynamic partial reconfigurable (DPR) capability, an FPGA fabric is no longer static; some of its regions can be dynamically reused for different tasks. Hence current software/hardware (HW/SW) partitioning approaches are no longer applicable to such reconfigurable hardware. This paper incorporates reconfiguration optimization into HW/SW partitioning targeting advanced region-based DPR design flow. Instead of analyzing the tasks for each time step, we introduce a new task graph representation with additional reconfiguration nodes so that the HW/SW partitioning for region-based DPR designs can be optimally solved efficiently by a novel mixed-integer linear programming (MILP) formulation. Experimental results show that our approach can obtain the optimal solutions 10 times faster than the current time-step based approach. For large designs which cannot be handled by the current approaches, our approach can achieve the optimum efficiently in reasonable runtime.