DocumentCode
174711
Title
Static thread mapping for NoCs via binary instrumentation traces
Author
Salvador, G. ; Nilakantan, S. ; Taskin, B. ; Hempstead, M. ; More, A.
Author_Institution
Univ. of Pennsylvania, Philadelphia, PA, USA
fYear
2014
fDate
19-22 Oct. 2014
Firstpage
517
Lastpage
520
Abstract
A novel methodology is proposed for thread mapping on a chip-multiprocessor (CMP) system with a network-on-chip (NoC). This novel mapping leverages multi-threaded traces produced by a binary instrumentation tool, which classifies the communication and computation events for each thread of a multi-threaded program application. Processing these binary instrumentation traces after profiling, a static thread mapping is computed to improve the NoC performance.
Keywords
microprocessor chips; multiprocessing systems; network-on-chip; NoC; binary instrumentation tool; binary instrumentation traces; chip-multiprocessor system; network-on-chip; static thread mapping; Aggregates; Benchmark testing; Bismuth; Instruction sets; Instruments; Monte Carlo methods; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design (ICCD), 2014 32nd IEEE International Conference on
Conference_Location
Seoul
Type
conf
DOI
10.1109/ICCD.2014.6974731
Filename
6974731
Link To Document