A unified DFT architecture for use with IEEE 1149.1 and VSIA/IEEE P1500 compliant test access controllers

Author

Dervisoglu, Bulent L.

Author_Institution

Cadence Design Syst. Inc., San Jose, CA, USA

fYear

2001

fDate

2001

Firstpage

53

Lastpage

58

Abstract

This paper discusses some of the critical issues that may prevent IEEE P1500 from becoming an acceptable standard and offers some suggestions for their solution. In particular, the inadequacy of the proposed P1500 and the VSIA solutions in handling hierarchical implementations is addressed. Support for hierarchical implementations is seen as an essential feature in a test access methodology that is intended for use in System on a Chip (SoC) designs. The author is actively pursuing some of these solutions through the working groups.

Keywords

IEEE standards; application specific integrated circuits; automatic testing; design for testability; industrial property; integrated circuit testing; logic testing; IEEE 1149.1; SoC designs; VSIA/IEEE P1500; hierarchical implementations; test access controllers; test access methodology; unified DFT architecture; working groups; Delay; Design for testability; Intellectual property; Permission; Proposals; Sockets; Standards development; System testing; System-on-a-chip; Virtual colonoscopy;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2001. Proceedings

ISSN

0738-100X

Print_ISBN

1-58113-297-2

Type

conf

DOI

10.1109/DAC.2001.156107

Filename

935476