Test volume and application time reduction through scan chain concealment

Author

Bayraktaroglu, Ismet ; Orailoglu, Alex

Author_Institution

Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA

fYear

2001

fDate

2001

Firstpage

151

Lastpage

155

Abstract

A test pattern compression scheme is proposed in order to reduce test data volume and application time. The number of scan chains that can be supported by an ATE is significantly increased by utilizing an on-chip decompressor. The functionality of the ATE is kept intact by moving the decompression task to the circuit under test. While the number of virtual scan chains visible to the ATE is kept small, the number of internal scan chains driven by the decompressed pattern sequence can be significantly increased.

Keywords

automatic test equipment; automatic test pattern generation; boundary scan testing; fault diagnosis; logic testing; sequential circuits; ATE; circuit under test; decompressed pattern sequence; decompression task; fault grading; functionality; internal scan chains; on-chip decompressor; scan chain concealment; sequential test generation; test application time; test pattern compression scheme; test volume; virtual scan chains; Application software; Automatic test pattern generation; Circuit faults; Circuit testing; Compaction; Computer science; Fault detection; Permission; Sequential analysis; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2001. Proceedings

ISSN

0738-100X

Print_ISBN

1-58113-297-2

Type

conf

DOI

10.1109/DAC.2001.156125

Filename

935494