Title :
Checking equivalence for partial implementations
Author :
Scholl, Christoph ; Becker, Bernd
Author_Institution :
Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
Abstract :
We consider the problem of checking whether a partial implementation can (still) be extended to a complete design which is equivalent to a given full specification. Several algorithms trading off accuracy and computational resources are presented: starting with a simple 0,1,X-based simulation, which allows approximate solutions, but is not able to find all errors in the partial implementation, we consider more and more exact methods finally covering all errors detectable in the partial implementation. The exact algorithm reports no error if and only if the current partial implementation conforms to the specification, i.e. it can be extended to a full implementation which is equivalent to the specification. We give a series of experimental results demonstrating the effectiveness and feasibility of the methods presented.
Keywords :
Boolean functions; VLSI; circuit CAD; circuit simulation; digital integrated circuits; error detection; formal verification; integrated circuit design; symbol manipulation; VLSI CAD; detectable errors; equivalence checking; exact algorithm; functional validation; partial implementations; specification conformance; verification; Aerospace industry; Boolean functions; Circuits; Computer science; Data structures; Educational institutions; Permission; State-space methods; Testing; Very large scale integration;
Conference_Titel :
Design Automation Conference, 2001. Proceedings
Print_ISBN :
1-58113-297-2
DOI :
10.1109/DAC.2001.156142