Title :
Improving bus test via IDDT and boundary scan
Author :
Yang, Shih-Yu ; Papachristou, Christos A. ; Taib-Azar, M.
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
This paper presents a systematic test methodology targeting bus line interconnect defects using IDDT testing and boundary scan. The traditional test is unable to detect all possible defects, especially timing-related faults. Open and short defects on interconnects between embedded modules can be detected by IDDT testing. Boundary scan can provide accessibility to internal buses. A statistical analysis is presented discussing the uncertain factors due to process variations and power fluctuation. The effectiveness of the proposed technique on shorts, opens or the other non stuck-at fault type defects is also illustrated.
Keywords :
CMOS integrated circuits; VLSI; boundary scan testing; built-in self test; electric current measurement; integrated circuit interconnections; integrated circuit testing; leakage currents; logic testing; statistical analysis; IDDT testing; boundary scan; built-in current sensor; bus line interconnect defects; bus test; embedded modules; internal buses; nonstuck-at fault type defects; open defects; power fluctuation; process variations; short defects; statistical analysis; test methodology; timing-related faults; CMOS logic circuits; Capacitors; Circuit testing; Current measurement; Driver circuits; Fabrication; Integrated circuit interconnections; Leakage current; Mirrors; Threshold voltage;
Conference_Titel :
Design Automation Conference, 2001. Proceedings
Print_ISBN :
1-58113-297-2
DOI :
10.1109/DAC.2001.156156
