Improving bus test via IDDT and boundary scan

This paper presents a systematic test methodology targeting bus line interconnect defects using I_DDT testing and boundary scan. The traditional test is unable to detect all possible defects, especially timing-related faults. Open and short defects on interconnects between embedded modules can be detected by I_DDT testing. Boundary scan can provide accessibility to internal buses. A statistical analysis is presented discussing the uncertain factors due to process variations and power fluctuation. The effectiveness of the proposed technique on shorts, opens or the other non stuck-at fault type defects is also illustrated.