DocumentCode :
1747934
Title :
Watermarking graph partitioning solutions
Author :
Wolfe, Greg ; Wong, Jennifer L. ; Potkonjak, Miodrag
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
fYear :
2001
fDate :
2001
Firstpage :
486
Lastpage :
489
Abstract :
Trends in the semiconductor industry towards extensive design and code reuse motivate a need for adequate intellectual property protection (IPP) schemes. We offer a new general IPP scheme called constraint-based watermarking and analyze it in the context of the graph partitioning problem. Graph partitioning is a critical optimization problem that has many applications, particularly in the semiconductor design process. Our IPP technique for graph partitioning watermarks solutions to graph partitioning problems so that they carry an author´s signature. Our technique is transparent to the actual CAD tool which does the partitioning. Our technique produces solutions that have very low quality degradation levels, yet carry signatures that are convincingly unambiguous, extremely unlikely to be present by coincidence, and difficult to detect or remove without completely resolving the partitioning problem.
Keywords :
VLSI; circuit CAD; circuit optimisation; copy protection; graph theory; industrial property; integrated circuit design; logic CAD; logic partitioning; CAD tool; constraint-based watermarking; graph partitioning solutions; intellectual property protection; optimization problem; quality degradation levels; semiconductor design process; semiconductor industry; Computer science; Degradation; Design automation; Design optimization; Electronics industry; Intellectual property; Permission; Process design; Protection; Watermarking;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2001. Proceedings
ISSN :
0738-100X
Print_ISBN :
1-58113-297-2
Type :
conf
DOI :
10.1109/DAC.2001.156188
Filename :
935557
Link To Document :
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