DocumentCode
1747968
Title
Timing analysis with crosstalk as fixpoints on complete lattice
Author
Zhou, Hai ; Shenoy, Narendra ; Nicholls, William
Author_Institution
Adv. Technol. Grou, Synopsys Inc., Mountain View, CA, USA
fYear
2001
fDate
2001
Firstpage
714
Lastpage
719
Abstract
Increasing delay variation due to crosstalk has a dramatic impact on deep sub-micron technologies. It is now necessary to include crosstalk in timing analysis. But timing analysis with crosstalk is a chicken-and-egg problem since crosstalk effect in turn depends on timing behavior of a circuit. In this paper, we establish a theoretical foundation for timing analysis with crosstalk. We show that solutions to the problem are fixpoints on a complete lattice. Based on that, we prove in general the convergence of any iterative approach. We also show that, starting from different initial solutions, an iterative approach will reach different fixpoints. The current prevailing practice, which starts from the worst case solution, will always reach the greatest fixpoint (which is the loosest solution). In order to reach the least fixpoint, we need to start from the best case solution. Based on chaotic iteration and heterogeneous structures of coupled circuits, we also design techniques to speed up iterations.
Keywords
VLSI; capacitance; crosstalk; integrated circuit design; integrated circuit interconnections; iterative methods; timing; wiring; chaotic iteration; complete lattice; coupled circuits; crosstalk; deep sub-micron technologies; delay variation; fixpoints; heterogeneous structures; iterative approach; timing analysis; timing behavior; Capacitance; Coupling circuits; Crosstalk; Delay; Integrated circuit noise; Iterative methods; Lattices; Switches; Timing; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2001. Proceedings
ISSN
0738-100X
Print_ISBN
1-58113-297-2
Type
conf
DOI
10.1109/DAC.2001.156230
Filename
935599
Link To Document