DocumentCode
1747977
Title
Timing driven placement using physical net constraints
Author
Halpin, Bill ; Chen, C. Y Roger ; Sehgal, Naresh
Author_Institution
Design Technol., Intel Corp., Santa Clara, CA, USA
fYear
2001
fDate
2001
Firstpage
780
Lastpage
783
Abstract
This paper presents a new timing driven placement algorithm that explicitly meets physical net lengths constraints. It is the first recursive bi-section placement (RBP) algorithm that meets precise half perimeter bounding box constraints on critical nets. At each level of the recursive bi-section, we use linear programming to ensure that all net constraints are met. Our method can easily be incorporated with existing RBP methods. We use the net constraint based placer to improve timing results by setting and meeting constraints on timing critical nets. We report significantly better timing results on each of the MCNC benchmarks and achieve an average optimization exploitation of 69% versus previously reported 53%.
Keywords
VLSI; circuit layout CAD; circuit optimisation; delays; integrated circuit layout; linear programming; logic CAD; network routing; timing; MCNC benchmarks; critical nets; half perimeter bounding box constraints; linear programming; net constraints; net lengths; optimization exploitation; physical net constraints; recursive bi-section placement algorithm; timing driven placement; timing results; Automatic control; Circuit optimization; Delay; Educational institutions; Integrated circuit interconnections; Linear programming; Partitioning algorithms; Permission; Timing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2001. Proceedings
ISSN
0738-100X
Print_ISBN
1-58113-297-2
Type
conf
DOI
10.1109/DAC.2001.156242
Filename
935611
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