Mismatch analysis and direct yield optimization by spec-wise linearization and feasibility-guided search

Author

Schenkel, Frank ; Pronath, Michael ; Zizala, Stephan ; Schwencker, Robert ; Graeb, Helmut ; Antreich, Kurt

Author_Institution

Inst. for Electron. Design Autom., Tech. Univ. Munchen, Germany

fYear

2001

fDate

2001

Firstpage

858

Lastpage

863

Abstract

We present a new method for mismatch analysis and automatic yield optimization of analog integrated circuits with respect to global, local and operational tolerances. Effectiveness and efficiency of yield estimation and optimization are guaranteed by consideration of feasibility regions and by performance linearization at worst-case points. The proposed methods were successfully applied to two example circuits for an industrial fabrication process.

Keywords

analogue integrated circuits; circuit optimisation; integrated circuit yield; linearisation techniques; tolerance analysis; analog integrated circuits; direct yield optimization; feasibility-guided search; global tolerances; industrial fabrication process; local tolerances; mismatch analysis; operational tolerances; performance linearization; spec-wise linearization; worst-case points; Circuit simulation; Design optimization; Electronic design automation and methodology; Fabrication; Integrated circuit yield; Optimization methods; Permission; Robustness; Threshold voltage; Yield estimation;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2001. Proceedings

ISSN

0738-100X

Print_ISBN

1-58113-297-2

Type

conf

DOI

10.1109/DAC.2001.156256

Filename

935625