An efficient expression of timestamp and period in packet-based and cell-based schedulers

Scheduling algorithms are implemented in hardware in high-speed switches to provision quality-of-service guarantees in both cell-based and packet-based networks. Being able to guarantee end-to-end delay and fairness, timestamp-based fair queuing algorithms have received much attention in the past few years. In timestamp-based fair queuing algorithms, the size of timestamp and period determines the supportable rates in terms of the range and accuracy. Furthermore, it also determines the scheduler´s memory in terms of off-chip bandwidth and storage space. An efficient expression can reduce the size of the timestamp and period without compromising the accuracy. We propose a new expression of the timestamp and period, which can be implemented in hardware for both high-speed packet-based and cell-based switches. As compared to fixed-point and floating-point number expression, when the size is fixed, the proposed expression has a better accuracy