• DocumentCode
    1748588
  • Title

    Locality vs. criticality

  • Author

    Srinivasan, Srikanth T. ; Ju, Roy Dz-ching ; Lebeck, Alvin R. ; Wilkerson, Chris

  • Author_Institution
    Dept. of Comput. Sci., Duke Univ., Durham, NC, USA
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    132
  • Lastpage
    143
  • Abstract
    Current memory hierarchies exploit locality of references to reduce load latency and thereby improve processor performance. Locality based schemes aim at reducing the number of cache misses and tend to ignore the nature of misses. This leads to a potential mis-match between load latency requirements and latencies realized using a traditional memory system. To bridge this gap, we partition loads as critical and non-critical. A load that needs to complete early to prevent processor stalls is classified as critical, while a load that can tolerate a long latency is considered non-critical. In this paper, we investigate if it is worth violating locality to exploit information on criticality to improve processor performance. We present a dynamic critical load classification scheme and show that 40% performance improvements are possible on average, if all critical loads are guaranteed to hit in the LI cache. We then compare the two properties, locality and criticality, in the context of several cache organization and prefetching schemes. We find that the working set of critical loads is large, and hence practical cache organization schemes based on criticality are unable to reduce the critical load miss ratios enough to produce performance gains. Although criticality-based prefetching can help for some resource constrained programs, its benefit over locality-based prefetching is small and may not be worth the added complexity
  • Keywords
    computational complexity; parallel processing; performance evaluation; storage management; cache misses; cache organization; complexity; critical load miss ratios; criticality; locality; memory hierarchies; prefetching; processor performance; processor stalls; Bridges; Cache memory; Computer science; Delay; Hardware; Memory management; Microprocessors; Performance gain; Prefetching; Random access memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture, 2001. Proceedings. 28th Annual International Symposium on
  • Conference_Location
    Goteborg
  • ISSN
    1063-6897
  • Print_ISBN
    0-7695-1162-7
  • Type

    conf

  • DOI
    10.1109/ISCA.2001.937442
  • Filename
    937442