DocumentCode
1748872
Title
A comprehensive examination of neural network architectures for analog fault diagnosis
Author
Aminian, Mehran ; Aminian, Farzan
Author_Institution
St. Mary´´s Univ., San Antonio, TX, USA
Volume
3
fYear
2001
fDate
2001
Firstpage
2304
Abstract
We have performed a detailed comparison of single-output and 1-of-k neural-network architectures used for analog fault diagnosis. Training and testing data are obtained from linear and nonlinear circuits simulated by SPICE. We have used wavelet and Fourier transforms, data normalization and principal component analysis to preprocess the node voltages and extract optimal features for training the neural networks. Comparison of the two architectures using the sample circuits reveal that 1) for circuits with overlapping features across fault classes, the 1-of-k is the superior architecture for analog fault diagnosis, 2) the 1-of-k architecture requires a significantly smaller training set to accurately diagnose faulty behavior, 3) because of its bigger size, the 1-of-k architecture imposes a high demand on computer resources and may become prohibitive for problems with large number of faults and 4) the training time per epoch is longer for the 1-of-k architecture but it requires a smaller number of epochs to reach the prespecified error goal. These results indicate that the 1-of-k architecture provides a more robust and stable analog fault diagnostic system unless it is prohibited by its increased demand on computer resources
Keywords
Fourier transforms; SPICE; analogue integrated circuits; fault diagnosis; feature extraction; linear network analysis; neural net architecture; nonlinear network analysis; principal component analysis; wavelet transforms; 1-of-k neural network architectures; Fourier transforms; SPICE; analog fault diagnosis; computer resources; data normalization; faulty behavior; linear circuits; neural network architectures; node voltages; nonlinear circuits; principal component analysis; single-output neural network architectures; training time per epoch; wavelet transforms; Analog computers; Circuit faults; Circuit simulation; Circuit testing; Computer architecture; Fault diagnosis; Neural networks; Nonlinear circuits; SPICE; Wavelet analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Neural Networks, 2001. Proceedings. IJCNN '01. International Joint Conference on
Conference_Location
Washington, DC
ISSN
1098-7576
Print_ISBN
0-7803-7044-9
Type
conf
DOI
10.1109/IJCNN.2001.938528
Filename
938528
Link To Document