Hardware implementation of an on-chip BP learning neural network with programmable neuron characteristics and learning rate adaptation

An analog on-chip backpropagation (BP) learning neural network with programmable neuron characteristics and learning rate adaptation is designed and fabricated with 1.2-μm CMOS, double-poly, double-metal technology. A novel neuron circuit with programmable parameters is proposed. It generates not only the sigmoid function but also its derivatives. Learning rate adaptation circuit is also presented to accelerate the convergence speed. The experiment of nonlinear partition is done and the result verifies the function of this on-chip BP learning neural network