Digital timing synchronization with jitter reduction technique for cap-based VDSL system

This paper describes a digital timing synchronization method for the CAP-based VDSL system. An adaptive loop filter with digitally controlled loop gain is proposed for jitter performance improvement. The proposed loop filter allows both fast locking and low steady state jitter. A digital spectral line method is used for robust timing extraction. Simulation results show that RMS timing jitter is less than 0.4% of the symbol period even for the worst case channel and synchronization is established within 400 symbol periods. The VDSL system is implemented in a 0.6 μm CMOS technology, and tested. The measured peak-to-peak timing jitter is about 0.1% of the symbol period, which makes the VDSL system receive data up to 52 Mbps over the telephone wire