DocumentCode
1749771
Title
Gigaop DSP on FPGA
Author
Hutchings, Brad L. ; Nelson, Brent E.
Author_Institution
Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
Volume
2
fYear
2001
fDate
2001
Firstpage
885
Abstract
DSP algorithms such as sonar beamforming and automated target recognition, are a good match for FPGA technology due to their regular structure, available parallelism, pipeline-ability, and modest data word sizes. FPGA implementations of these applications outperformed their DSP and microprocessor counterparts by factors ranging from 10X on up with an equivalent sustained computational rate of more than 2 GOps/second per FPGA. This paper first describes each application and derives its computational requirements. The mapping process for each is then described followed by an analysis of the relative contributions to performance from pipelining, data parallelism, and memory usage
Keywords
array signal processing; field programmable gate arrays; mathematical morphology; parallel algorithms; pipeline processing; radar signal processing; sonar signal processing; sonar target recognition; DOA estimation; DSP algorithms; Gigaop DSP; automated target recognition; binary images; binary morphology; data parallelism; data word size; direction-of-arrival; mapping process; memory usage; microprocessor; parallel structure; passive beamforming; pipeline structure; regular structure; sonar beamforming; Circuits; Concurrent computing; Digital signal processing; Electronics packaging; Field programmable gate arrays; Interference; Parallel processing; Scheduling algorithm; Sonar; Target recognition;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, 2001. Proceedings. (ICASSP '01). 2001 IEEE International Conference on
Conference_Location
Salt Lake City, UT
ISSN
1520-6149
Print_ISBN
0-7803-7041-4
Type
conf
DOI
10.1109/ICASSP.2001.941057
Filename
941057
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