Vector processing in scalar processors for signal processing algorithms

Author

Brady, Michael T. ; Trelewicz, J.Q. ; Mitchell, Joan L.

Author_Institution

Printing Syst. Div., IBM Corp., Boulder, CO, USA

Volume

2

fYear

2001

fDate

2001

Firstpage

933

Abstract

Product requirements often dictate the use of off-the-shelf processors for very fast signal processing applications. Additionally, restrictions on cost, power, or size/weight may preclude the use of specialized vector processors for implementation of the algorithms. We discuss a new method for performing signed parallel processing in scalar, off-the-shelf processors for integerized signal processing algorithms. Uniform data precision may be used, but is not required for the method. It is shown that the reduction in execution cycles resulting from this implementation is approximately linear in the size of the registers, divided by the precision required

Keywords

parallel processing; signal processing; vector processor systems; execution cycles; implementation; integerized signal processing algorithms; register size; scalar processors; signed parallel processing; uniform data precision; vector processing; Arithmetic; Costs; Discrete cosine transforms; Linear approximation; Parallel processing; Printing; Registers; Road transportation; Signal processing algorithms; Vector processors;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 2001. Proceedings. (ICASSP '01). 2001 IEEE International Conference on

Conference_Location

Salt Lake City, UT

ISSN

1520-6149

Print_ISBN

0-7803-7041-4

Type

conf

DOI

10.1109/ICASSP.2001.941069

Filename

941069