A 333-MHz dual-MAC DSP architecture for next-generation wireless applications

Author

Kolagotla, Ravi K. ; Fridman, Jose ; Hoffman, Marc M. ; Anderson, William C. ; Aldrich, Bradley C. ; Witt, David B. ; Allen, Michael S. ; Dunton, Randy R. ; Booth, Lawrence A., Jr.

Author_Institution

Analog Devices, Intel Joint DSP Dev. Center, Austin, TX, USA

Volume

2

fYear

2001

fDate

2001

Firstpage

1013

Abstract

We introduce the first DSP core developed at the Analog Devices and Intel Joint DSP Development Center. The 16-bit fixed-point core combines some of the best features of traditional DSPs and micro-controllers and compares favorably with dual-MAC DSPs on DSP specific benchmarks and with micro-controllers on micro-controller specific benchmarks. In addition, the core supports a rich set of alignment independent packed byte instructions to enable an efficient implementation of 3G algorithms in next-generation wireless applications. The deep and fully interlocked pipeline allows the core to run at 333-MHz in the 0.18-μm TSMC process

Keywords

digital signal processing chips; fixed point arithmetic; microcontrollers; radio equipment; 0.18 micron; 333 MHz; 3G algorithms; Analog Devices; DSP core; Intel Joint DSP Development Center; TSMC process; alignment independent packed byte instructions; dual-MAC DSP architecture; fixed-point core; interlocked pipeline; microcontrollers; next-generation wireless applications; Algorithm design and analysis; Convergence; Costs; Digital signal processing; Hardware; Pipelines; Random access memory; Registers; System buses; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 2001. Proceedings. (ICASSP '01). 2001 IEEE International Conference on

Conference_Location

Salt Lake City, UT

ISSN

1520-6149

Print_ISBN

0-7803-7041-4

Type

conf

DOI

10.1109/ICASSP.2001.941089

Filename

941089