An integrated systolic array design for video compression

This paper presents an integrated systolic array design for implementing full-search block matching, 2-D discrete wavelet transform, and full-search vector quantization on the same VLSI architecture. The above three functions are prime essential but with a large amount of computation in video compression. To meet real-time requirements, many systolic arrays are designed for individually performing each of them. In fact, these functions contain the similar computational procedure. The matrix-vector product forms of them are quite similar. In this paper, by carefully extracting the common computation component, an integrated systolic array design that can perform the above three functions is presented. A utilization of 100% to 97% is achieved for executing full-search block matching and full-search vector quantization. When performing the 2-D discrete wavelet transform, the utilization is about 32%. The proposed integrated architecture has lower hardware cost and has a a regular hardware structure. It befits the VLSI implementation for video compression