Decision feedback equalizer with two´s complement computation sharing multiplication

Author

Choo, Hunsoo ; Muhammad, Khurram ; Roy, Kaushik

Author_Institution

Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA

Volume

2

fYear

2001

fDate

2001

Firstpage

1245

Abstract

We present an architecture of a high performance decision feedback equalizer based on a computation sharing multiplier. The computation sharing multiplier (CSHMR) uses a redundant number scheme and targets removal of computational redundancy by computation re-use. Use of CSHMR leads to high performance FIR filtering operation by re-using optimal precomputations. A decision feedback equalizer (DFE) implementation based on CSHMR in a 0.35 μ technology shows 34% improvement in the operating speed over DFE using a Wallace tree multiplier

Keywords

FIR filters; decision feedback equalisers; multiplying circuits; redundant number systems; 0.35 micron; FIR filtering; computation re-use; computation sharing multiplier; decision feedback equalizer; optimal precomputations; redundant number scheme; two complement computation sharing multiplication; Arithmetic; Computer architecture; Decision feedback equalizers; Filtering; Finite impulse response filter; High performance computing; Instruments; Nonlinear filters; Propagation delay; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 2001. Proceedings. (ICASSP '01). 2001 IEEE International Conference on

Conference_Location

Salt Lake City, UT

ISSN

1520-6149

Print_ISBN

0-7803-7041-4

Type

conf

DOI

10.1109/ICASSP.2001.941150

Filename

941150