Damascene processing of ferroelectric capacitors

A unique, single-step damascene approach was used to form ferroelectric capacitors with noble metal electrodes. In this study an oxidized Si substrate was coated with a blanket W film and a patterned SiO₂ film. Capacitors were formed by conformal deposition of a sputtered bottom electrode structure (100 nm Ir/50 nm TiAlN), MOCVD ferroelectric (130 nm (Pb,Ca)ZrTiO₃), and sputtered top electrode (150 nm Ir). A halide-based slurry was used in a single multi-layer polish to define planar, recessed capacitors between 100×100 μm² and 10×10 μm². The Ir removal rate was 14 nm/minute. Annealed capacitors had ferroelectric and dielectric properties that were similar to conventionally processed capacitors. 2P_r and switched charge at 2V were found to be 42 μC/cm² and 40 μC/cm² respectively with a leakage current density of 10^-4 A/cm² at 2V