A 12GHz 67% tuning range 0.37pS RJrms PLL with LC-VCO temperature compensation scheme in 0.13μm CMOS

This paper presents a PLL designed in 0.13μm CMOS for multi-data rate serial link applications. A novel temperature compensation scheme is proposed to reduce the LC-VCO temperature frequency drift without sacrificing the tuning range. Thus, the PLL covers a 5.6GHz to 13.4GHz tuning range by using just two VCO cores while remaining locked from -40°C to 85°C. At 25°C, the PLL has an RMS random jitter (RJ_rms) of 0.37pS at 11.44GHz. The integrated jitter is less than 0.7pS over the tuning range and varies less than 50fS over temperature. The PLL consumes 50.88mW of power from a 1.2V supply at 12GHz and 25°C.