Broadband CMOS stacked power amplifier using reconfigurable interstage network for envelope tracking application

A 2-stage stacked-FET power amplifier with a reconfigurable interstage network is developed for broadband envelope tracking application using SOI CMOS. The wideband PA is based on Class-J mode of operation, where output matching is realized with two-section low-pass network. Miller capacitors are also employed across the FET stack to guarantee Class-J-like operation for inner FET stacks. To overcome the bandwidth limit due to high-Q interstage matching, reconfigurable matching network is employed using SOI switch, allowing dual frequency-mode operation. The fabricated PA shows CW efficiencies in excess of 60% from 0.65 to 1.0 GHz. When operated with an ET supply modulator, overall ET PA system shows W-CDMA efficiencies higher than 50% from 0.68 to 0.92 GHz and LTE efficiencies higher than 40% from 0.65 to 0.95 GHz.