DocumentCode :
175198
Title :
A fully-integrated 18 GHz class-E power amplifier in a 45 nm CMOS SOI technology
Author :
Jing-Hwa Chen ; Helmi, S.R. ; Jou, Alice Yi-Szu ; Mohammadi, Soheil
Author_Institution :
Purdue Univ., West Lafayette, IN, USA
fYear :
2014
fDate :
1-3 June 2014
Firstpage :
247
Lastpage :
250
Abstract :
A fully-integrated Class-E power amplifier (PA) operating at 18 GHz is implemented in a standard 45 nm CMOS SOI technology. The PA is designed using differential Cascode topology with cross-coupled capacitors for Gate-Drain capacitance neutralization. The measured single-ended saturated power (PSAT) under a supply voltage of 2 V is 15.9 dBm (differential PSAT of 18.9 dB) and the 1-dB single-ended compression power (P1dB) is 13.3 dBm, with a peak power added efficiency (PAE) of 41.4%. The GateDrain capacitance neutralization technique facilitates the class-E operation and improves the PAE by ~20%.
Keywords :
CMOS analogue integrated circuits; MMIC power amplifiers; integrated circuit design; silicon-on-insulator; CMOS SOI technology; Si; cross-coupled capacitors; differential cascode topology; efficiency 41.4 percent; frequency 18 GHz; fully-integrated Class-E PA; fully-integrated class-E power amplifier design; gate-drain capacitance neutralization technique; measured single-ended saturated power; peak power added efficiency; single-ended compression power; size 45 nm; voltage 2 V; CMOS integrated circuits; CMOS technology; Capacitance; Capacitors; Power amplifiers; Power generation; Voltage measurement; CMOS; Class-E; K-band; RF power amplifier; SOI;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Radio Frequency Integrated Circuits Symposium, 2014 IEEE
Conference_Location :
Tampa, FL
ISSN :
1529-2517
Print_ISBN :
978-1-4799-3862-9
Type :
conf
DOI :
10.1109/RFIC.2014.6851710
Filename :
6851710
Link To Document :
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