A 25Gbps, 2x-oversampling CDR using a zero-crossing linearizing phase detector

A 2x-oversampling 25Gbps clock and data recovery (CDR) circuit is proposed that employs a charge-based, zero-crossing linearizing phase detector (ZCL-PD). This technique linearizes the conventional bang-bang CDR system, resulting in low quantization jitter, improved loop bandwidth, and improved input sensitivity. To minimize the power consumption, an injection-locked inverter-based 1:2 divider reduces CML clocking power while maintaining low jitter. The 65nm-CMOS test-chip measurements demonstrate error-free operation for PRBS-7 and PRBS-31, an 120mV differential input sensitivity, a 9MHz jitter transfer bandwidth, 1.08ps/9.63ps (rms/pk-pk) of recovered clock jitter, and 65mW of power consumption.