Title :
A 25Gb/s 170μW/Gb/s optical receiver in 28nm CMOS for chip-to-chip optical communication
Author :
Saeedi, Saeed ; Emami, Ali
Author_Institution :
Dept. of Electr. Eng., California Inst. of Technol., Pasadena, CA, USA
Abstract :
A low-power high-speed optical receiver in 28nm CMOS is presented. The design features a novel architecture combining a low-bandwidth TIA front-end, double-sampling technique and dynamic offset modulation. The low-bandwidth TIA increases receiver´s sensitivity while adding minimal power overhead. Functionality of the receiver was validated and the design is compared with a conventional 3-stage TIA receiver via actual measurements. The proposed receiver architecture achieves error-free operation (BER<;10-12) at 25Gb/s with energy efficiency of 170fJ/b while the conventional receiver achieves error-free operation at 17.1Gb/s with energy efficiency of 260fJ/b.
Keywords :
CMOS integrated circuits; integrated circuit design; low-power electronics; optical communication; optical receivers; 3-stage TIA receiver; CMOS process; bit rate 17.1 Gbit/s; bit rate 25 Gbit/s; chip-to-chip optical communication; double-sampling technique; dynamic offset modulation; low-bandwidth TIA front-end; low-power high-speed optical receiver; size 28 nm; Bandwidth; CMOS integrated circuits; Modulation; Optical receivers; Optical sensors; Sensitivity; high-speed transceivers; hybrid integrated circuits; optical interconnection; sampled-data circuits;
Conference_Titel :
Radio Frequency Integrated Circuits Symposium, 2014 IEEE
Conference_Location :
Tampa, FL
Print_ISBN :
978-1-4799-3862-9
DOI :
10.1109/RFIC.2014.6851720
