Title :
Design of a power-scalable digital least-means-square adaptive filter
Author :
Ng, CheeWe ; Chandrakasan, Anantha P.
Author_Institution :
Microsystems Technol. Lab., MIT, Cambridge, MA, USA
Abstract :
Channel equalization is a required function in many high speed communication systems. As a result of the high performance requirements and complexity, adaptive equalization filters require significant power. These filters are often implemented in hardware rather than software on a DSP. A power scalable adaptive equalizer is presented where the power scales with the required precision through the use of dynamic tap length and bit precision. Using these techniques, a power reduction from 20.4 mW in a fixed length and bit precision filter to a minimum of 6.4 mW is demonstrated
Keywords :
CMOS digital integrated circuits; adaptive equalisers; adaptive filters; digital filters; digital signal processing chips; least mean squares methods; network synthesis; 6.4 mW; DSP; ISI-cancellation; LMS adaptive filter; adaptive equalization filters; bit precision; bit precision filter; channel equalization; control logic; digital CMOS; dynamic tap length; fixed length filter; high speed communication systems; least-means-square adaptive filter; power reduction; power scalable adaptive equalizer; power-scalable digital filter design; Adaptive equalizers; Adaptive filters; Adaptive signal processing; Decision feedback equalizers; Digital signal processing; Interference; Iterative algorithms; Least squares approximation; Power filters; Signal processing algorithms;
Conference_Titel :
Signal Processing and its Applications, Sixth International, Symposium on. 2001
Conference_Location :
Kuala Lumpur
Print_ISBN :
0-7803-6703-0
DOI :
10.1109/ISSPA.2001.949835