DocumentCode
1752297
Title
Reducing test time via an optimal selection of LFSR feedback taps
Author
Afaq, Ahmad ; Al-Lawati, Ali
Author_Institution
Coll. of Eng., Sultan Qaboos Univ., Muscat, Oman
Volume
1
fYear
2001
fDate
2001
Firstpage
300
Abstract
The results of a simulation study demonstrate that in linear feedback shift register-based built-in VLSI testing, the selection of proper feedback taps can reduce the test application time while retaining the testability goals
Keywords
VLSI; built-in self test; circuit feedback; circuit optimisation; circuit simulation; design for testability; shift registers; LFSR; VLSI; built-in testing; feedback taps; linear feedback shift register; optimal selection; simulation study; test application time; testability; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Digital systems; Linear feedback shift registers; Polynomials; Signal processing; System testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing and its Applications, Sixth International, Symposium on. 2001
Conference_Location
Kuala Lumpur
Print_ISBN
0-7803-6703-0
Type
conf
DOI
10.1109/ISSPA.2001.949837
Filename
949837
Link To Document