A novel simulation and verification approach in an ASIC design process

Author

Husmann, D. ; Keller, M. ; Mahboubi, K. ; Pfeiffer, U. ; Schumacher, C.

Author_Institution

Kirchhoff-Inst. fur Phys., Heidelberg Univ., Germany

Volume

2

fYear

2000

fDate

2000

Firstpage

42724

Abstract

We have built a fast signal-processing and readout ASIC (PPrAsic) for the Pre-Processor system of the ATLAS Level-1 Calorimeter Trigger. Our novel ASIC design environment incorporates algorithm development with digital hardware synthesis and verification. The purely digital ASIC was designed in Verilog HDL (hardware description language) and embedded in a system wide analog and digital simulation or implemented algorithms. We present here our design environment and experience that we gained from the design process

Keywords

application specific integrated circuits; digital readout; hardware description languages; nuclear electronics; trigger circuits; ASIC design process; ATLAS Level-1 Calorimeter Trigger; PPrAsic; Pre-Processor system; Verilog HDL; algorithm development; digital hardware synthesis; digital hardware verification; fast signal-processing and readout ASIC; hardware description language; purely digital ASIC; Algorithm design and analysis; Application specific integrated circuits; Calorimetry; Delay; Hardware design languages; Mesons; Process design; Signal processing; Signal processing algorithms; Signal synthesis;

fLanguage

English

Publisher

ieee

Conference_Titel

Nuclear Science Symposium Conference Record, 2000 IEEE

Conference_Location

Lyon

ISSN

1082-3654

Print_ISBN

0-7803-6503-8

Type

conf

DOI

10.1109/NSSMIC.2000.949932

Filename

949932